1. Field of the Invention
The present invention relates to the structure of a semiconductor device and a manufacturing method thereof, and more especially relates to the structure of a Dynamic-Threshold Voltage MOSFET (DTMOSFET) built on a Silicon-On-Insulator (SOI) substrate and a manufacturing method thereof.
2. Description of the Background Art
Among MOSFETs on SOI, DTMOSFETs (hereinafter referred to as "DTMOSs") have been proposed as means for increasing operating speed. FIG. 42 is a cross-sectional view schematically showing the structure of a conventional DTMOS on SOI (cf. Assaderaghi et al., "A Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra-Low Voltage Operation", IEDM 94-811, FIG. 1a). An SOI substrate 101 has a multilayer structure with a silicon substrate 102, a buried oxide film 103, and an SOI layer 104 stacked in this order. On the upper surface of the SOI layer 104, a multilayer gate structure is selectively formed, wherein a gate oxide film 105 and a gate electrode 106 are stacked in this order. In the upper surface of the SOI layer 104, a pair of source/drain regions 108 are formed to sandwich a body region 107 located under the gate structure. The gate electrode 106 and the body region 107 are electrically connected to each other.
FIG. 43 is a graph showing the relationships between body potential V.sub.B and operating threshold voltage V.sub.TH of a DTMOS transistor taken as an NMOS. When the transistor is turned on with a HIGH on the gate, the body potential V.sub.B correspondingly goes HIGH. This lowers the operating threshold voltage V.sub.TH as shown in FIG. 43, resulting in a larger current flow than a standard MOSFET on SOI.
FIG. 44 is a top view specifically showing the structure of the DTMOS in FIG. 42, and FIG. 45 is a cross-sectional view of the DTMOS in FIG. 44 taken along the line X1 (cf. Assaderaghi et al., "A Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra-Low Voltage Operation", IEDM94-811, FIG. 1b). The gate electrode 106 includes an electrode portion 106A above the body region 107 sandwitched between the pair of source/drain regions 108, and a wider pad portion 106B connected to the electrode portion 106A. An element isolation insulation film 109 is formed by LOCOS to surround the source/drain regions 108 and the pad portion 106B. The bottom surface of the element isolation insulation film 109 reaches the upper surface of the buried oxide film 103. That is, the element isolation insulation film 109 achieves so-called "complete isolation". In the middle of the pad portion 106B, a conductor-filled contact hole 110 is formed, extending through the gate oxide film 105 to the upper surface of the SOI layer 104. A conductor 112 filling the contact hole 110, such as Al, provides electrical connections between the gate electrode 106 and a p.sup.+ -type region 111 which is selectively formed in the body region 107.
In such a conventional DTMOS, however, there is only a small distance between the pad portion 106B and the SOI layer 104 (body region 107). This causes high parastic capacitance therebetween, which is added to gate capacitance, thereby increasing delay in operation.